The present invention relates to a method for forming a wiring pattern of a semiconductor integrated circuit, and more particularly, to a method for forming a wiring pattern of a semiconductor integrated circuit including a plurality of circuit modules.
When designing a semiconductor integrated circuit device, a plurality of module sections at which modules are arranged are first defined on a semiconductor substrate. Then, a plurality of circuit elements are arranged in each of the module sections to form a module in each module section. Afterward, the layout of signal lines for transferring data and power lines for supplying power to each of the modules is designed.
The wiring of the signal and power lines are designed for each circuit net, which is provided with the same signal and/or power. Thus, when two nets are located on the same wiring layer, the signal and power supply lines of one net may interfere with the signal and power supply lines of the other net. FIG. 1 shows an example of a power supply line connection. A first middle line 71, which supplies power VDD, and a second middle line 72, which supplies power VSS, which potential differs from power VDD, are arranged on a lower wiring layer LB. A left line 73 and right lines 74 for supplying power are arranged on an upper wiring layer LC. When connecting the left line 73 and the first middle line 71 and the right line 74 and the second middle line 72, the left and right power supply lines 73, 74 interfere with each other on the upper wiring layer LC.
Therefore, in a first prior art wiring method, right bent lines 74a are arranged on the upper wiring layer LC to avoid the left line 73, as shown in FIG. 2. This enables connection of the left power supply line 73 to the first middle line 71 and the connection of the right bent lines 74a to the second middle line 72. Alternatively, as shown in FIG. 3, a left bent line 73a may be arranged on the upper wiring layer LC to avoid the right lines 74.
A second prior art wiring method is shown in FIG. 4. Right lines 74b, 74c, 74d are arranged on wiring layers LC, LB, LA, respectively. The line 74d extends beneath the first middle line 71 and is connected to the second middle line 72.
Alternatively, as shown in FIG. 5, left lines 73b, 73c, 73d may be arranged on the wiring layers LC, LB, LA, respectively. The line 73d extends beneath the second middle line 72 and is connected to the first middle line 71.
The first and second wiring methods were also combined in the prior art.
However, in the prior art methods, for example, a clearance must be provided about a line even if the width and capacity of the line is greater than necessary. This decreases the area available for other lines. Although this would cause no problem if the semiconductor substrate has sufficient space, this does cause problems if other power and signal lines or cell patterns already occupy the substrate. In such case, the space for avoiding other lines is insufficient. Further, since line bonding is hindered, the layout of peripheral circuits must be redesigned. This prolongs the design time and increases the circuit area and the chip dimension.
It is an object of the present invention to provide a method for designing a wiring pattern of a semiconductor integrated circuit that connects a plurality of lines having different potentials within a small area.
To achieve the above object, the present invention provides a method for forming a wiring pattern of a semiconductor integrated circuit including a first line for conducting to a first potential and a second line for conducting to a second potential. The method includes detecting a portion of a distal end of the first line that overlaps a distal end of the second line, and generating a first avoidance pattern by eliminating the overlapping portion from the first line.
A further aspect of the present invention provides an apparatus for forming a wiring pattern of a semiconductor integrated circuit including a first line for conducting a first potential and a second line for conducting a second potential. The apparatus includes a detector for detecting a portion of a distal end of the first line that overlaps a distal end of the second line, and a processor including an avoidance pattern generator for generating a first avoidance pattern by eliminating the overlapping portion from the first line.
Another aspect of the present invention provides a computer readable storage medium storing a program for forming a wiring pattern of a semiconductor integrated circuit including a first line for conducting a first potential and a second line for conducting a second potential. The program includes the steps of detecting a portion of a distal end of the first line that overlaps a distal end of the second line, and generating a first avoidance pattern by eliminating the overlapping portion from the first line.
A further aspect of the present invention provides a semiconductor integrated circuit device including a first power line for conducting a first potential, a second power line for conducting a second potential, which differs from the first potential, and arranged parallel to the first power line, a third power line extending transversely to the second power line and connected to the first power line, and a fourth power line extending transversely to the first power line and connected to the second power line. The third power line has a plurality of distal portions including a first distal portion and a second distal portion, and the fourth power line has a distal portion arranged between the first and second distal portions.
Another aspect of the present invention provides a method for connecting lines in a semiconductor integrated circuit including a first line for conducting a first potential, a second line for conducting a second potential, a third line for conducting the first potential, and a fourth line for conducting the second potential. The first and second lines are arranged on a first layer, and the third and fourth lines are arranged on a second layer. The first line is connected to the third line, and the second line is connected to the fourth line. The method includes detecting a portion of a distal end of the third line that overlaps a distal end of the fourth line, generating a first avoidance pattern by eliminating the overlapping portion from the third line, temporarily storing data of the first avoidance pattern in a memory, determining whether the first avoidance pattern satisfies a predetermined wiring requirement, forming a new third line having the first avoidance pattern when the wiring requirement is satisfied, and forming via holes connecting the first line to the new third line and the second line to the fourth line.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.